Enhancing RISC-V Performance Analysis Infrastructure
summary
Describes concrete ISA and software changes: adds privilege-mode filtering to mcycle/minstret, introduces supervisor counter delegation plus indirect CSR to let S-mode write counters, extends SBI for a PMU snapshot shared-memory read and a supervisor software event to bypass IRQs, and a Control Transfer Records TG for branch history. Results: reduces ecall traps from ~9x to zero or 5x in virtualization, saves ~15,000 ecalls on a ping‑pong workload, and cuts ~50% of instructions in interrupt delivery. Integrates with Linux perf, KVM, JSON PMU bindings.
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chapters (7)
- 0:00Performance analysis overview
- 1:31Security and counter access
- 2:57Reducing profiling overhead
- 4:44Virtualization optimizations
- 11:18Handling kernel blind spots
- 13:14Event standardization
- 15:46Future work and roadmap
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