Demo: Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions

on YouTube ↗12m

" summary

Extends the RISC‑V Vector ISA with three custom ops: BLRS vector load with row stride, matrix‑multiply (with or without accumulation) and BSTS vector store with row stride; multiplies 16‑bit inputs (BF16) into FP32 accumulators using a tile‑based approach that keeps tiles in existing vector registers. Inner GEMM loop compiles to about eight assembly instructions. Demo reports up to near‑peak throughput on YOLOv3‑tiny layers, peak claimed as 256 MACs/cycle ⇒ 0.5 TOPS at 1 GHz, and shows reduced efficiency on small or non‑aligned tiles due to tail iterations.

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" chapters (5)

1. 0:00Introduction to tensor units
2. 1:03Custom tensor instructions
3. 3:00Implementing matrix math
4. 7:25Performance results
5. 8:36Q&A session

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