State of the Union for Olympia: A RISC-V OoO Processor Model for Community-Use

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" summary

Open-source, trace-driven cycle-approximate model of an example RISC-V superscalar processor built on the Sparta C++ framework and hosted on GitHub (≈2,000 views, ~190 clones, ~40 PRs, ~12 active contributors). Implements physical register rename and out-of-order load/store execution, non-blocking d-cache with refill, multiple core configs (small/medium/big) for IPC studies, unit tests, CI/regressions and a conda build environment. Ongoing: vector unit, L2 and memory subsystem, cache-replacement/branch-predictor APIs and SystemC interfacing.

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" chapters (7)

1. 0:00Introduction to Olympia
2. 1:03What is Olympia
3. 3:11State of Olympia last year
4. 4:36Recent improvements
5. 8:21Community and future plans
6. 13:22Current status and call for help
7. 14:49Q&A

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