RGen: A Sail Extension for Generating RISC-V Compiler, Simulator, and Application Support

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" summary

Claim: an open-source Sail extension called RGen generates end-to-end tool support from Sail to compiler, simulator, and application layers. It adds a high-order-op language RGenIR, extends Sail frontend/backends, and emits LLVM TableGen, QEMU (via KVM/Spike-style) decoder and tiny-codegen stubs, and PyTorch operator glue. A matrix-extension prototype is generated, cross-compiled into PyTorch, and runs on an emulated RISC-V setup within minutes with correct execution and promising performance.

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" chapters (9)

1. 0:00Problem statement
2. 1:51Argin project overview
3. 2:33Target artifacts design
4. 4:13Technical implementation
5. 7:16Argin architecture and IR
6. 11:17LLVM support generation
7. 13:32QEMU simulator support
8. 15:14PyTorch application support
9. 16:41Performance and conclusion

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