Sail RISC-V: Status and Future Challenges
summary
Sail is the RISC‑V golden model language with RV32/RV64 core, Vector and many Z extensions implemented, and a proof‑of‑concept for runtime configurability (no recompiles) built using JSON key/value configs. A module system exists to include or exclude extensions; hypervisor support is still missing and is hard because it touches CSRs and instructions. Tools produce an ISS, SystemVerilog translation, Asciidoctor docs, and a plan for native Sail floating‑point to replace C libs; 18 active contributors and a backlog of PR reviews remain.
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chapters (6)
- 0:00Introduction and golden model
- 2:46Understanding the Sail language
- 5:02Sail architecture and status
- 11:21Project goals and documentation
- 13:54Model configurability
- 17:42Memory ordering and conclusion
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16mAutomatic Test Generation and Verification for RISC-V Vector Extension
18mRGen: A Sail Extension for Generating RISC-V Compiler, Simulator, and Application Support
26mArchSem: Reusable Rigorous Semantics of Relaxed Architectures
20mRISC V Software State of the Union
