Demo: Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips

on YouTube ↗11m

" summary

Demo shows Lauterbach Trace32 controlling heterogeneous cores on a Zynq UltraScale+ MPSoC with four Cortex‑A53, two RISC‑V R5 and a MicroBlaze plus FPGA fabric, using the RISC‑V external debug DTM/DMI to present one debug interface and one debug probe to the system. Cross‑triggering uses ARM CTI to start/stop cores synchronously or run them independently; on‑ and off‑chip real‑time trace for major RISC‑V trace systems collects execution streams. OS awareness decodes Linux, Zephyr and FreeRTOS contexts so multicore trace and debug work end‑to‑end.

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" chapters (9)

1. 0:00Introduction
2. 0:12Challenges
3. 1:08External Debug Spec
4. 2:17Debug Module
5. 3:37Debug Environment
6. 5:11Why Trace
7. 7:13Risk 5 and Trace
8. 8:39OS Awareness
9. 9:56Summary

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