Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips
summary
Shows a working Lauterbach setup that controls RISC-V and Cortex cores through a single debug path using the RISC-V debug module + DTM over JTAG or an on‑chip AXI access port, with external triggers to break cores in sync. Demonstrates real‑time trace from two RISC-V harts into a trace encoder feeding a message infrastructure, offloading via USB Communicator or Aurora, and a trace communicator that bridges RISC‑V trace into a CoreSight ATB so traces from different ISAs merge and are filtered to avoid congestion.
AI-written summary · about
chapters (11)
- 0:00Introduction to talk
- 0:25Debugging challenges in complex chips
- 1:31RISC-V debug specification overview
- 2:40Debugging heterogeneous systems
- 3:01First demo setup explanation
- 4:51Trace benefits for real-time debugging
- 5:55Trace specifications for RISC-V
- 6:59Trace infrastructure for heterogeneous systems
- 7:43Third demo setup and trace offloading
- 8:47Key takeaways and future work
- 9:30Q&A session
related talks
11mDemo: Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips
14mRISC-V Debugging: Custom ISA Extensions, Multicore, DTM Variants
12mDemo: RISC-V 64 Bit Debug and Trace
02h 00mAdvanced Debug and Trace Tools for RISC-V Architectures
16mEfficient debug and trace of RISC-V systems: a hardware/software co-design approach
11mDemo: Ashling’s Vitra-XS Debug & Trace Probe for Embedded Development with Support for RISC-V Target Architectures
09mDemo: Accelerate RISC-V Development with Tessent UltraSight-V
11mBoost SoC Debug with Smart Monitors and Embedded Software