Boost SoC Debug with Smart Monitors and Embedded Software
summary
Shows embedding a suite of RDL monitors (including a RISC‑V enhanced trace encoder offering cycle-accurate instruction trace) and using a bus monitor to compute min/max/avg cache traffic; a 5G customer finds three simultaneous memory initiator collisions that cause memory degradation and measurable CPU performance loss; on‑chip preprocessing and Tessent Embedded SDK run edge analytics that sends only relevant events, enables real‑time error detection and telemetry, and supports field software upgrades to fix issues observed in the wild.
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chapters (9)
- 0:00Introduction to SoC debug challenges
- 1:52What are smart monitors
- 3:37RiskFive trace encoder features
- 4:20Customer case study with 5G SoC
- 6:06Tessent embedded SDK overview
- 7:10Edge analytics with monitors
- 7:52Real-time error detection
- 8:34Continuous hardware telemetry
- 9:38Summary and benefits
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