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Demo: RISC-V 64 Bit Debug and Trace

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Demo shows Lauterbach tools: X50 debugger, PowerTrace III and PowerTrace Serial collecting RISC‑V 64‑bit Nexus/Tessent trace with planned N‑Trace/E‑Trace support once ratified. Software uses trace‑list and chart views on a FreeRTOS trace to timestamp events, revealing a recurring timer with exact 1 ms intervals but occasional 1 millisecond jitter up to ~1.1 ms and sporadic missed ticks; mixed RISC‑V/ARM systems are supported via CoreSight/TPIU and cores can be time‑correlated with a common timestamp.

AI-written summary · about

  1. 0:00Introduction and overview
  2. 0:34Debug and trace solutions
  3. 6:16Software analysis and demo
  4. 9:14Statistical analysis and Q&A
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