Visualizing and Recording the true Runtime Behavior of a RISC V based App
summary
SEGGER demonstrates a live toolchain that extracts runtime events from RISC-V cores using SEGGER RTT over a J-Link probe and visualizes them in SystemView. Claims: typical text line out in ~1 microsecond, timestamp resolution down to one CPU cycle (≈5 ns at 200 MHz), <2 KB ROM and ≈600 bytes RAM overhead, about 1% runtime impact, configurable buffer, and recording with dropped-frame indicators. Requires RISC-V debug block with system bus access; works on tested RD board.
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chapters (20)
- 0:00Introduction
- 0:19Agenda
- 1:04About Segar
- 1:31Product Groups
- 2:14Typical Application
- 3:40Visualizing Recording
- 4:33The Elements
- 5:14The Solution
- 6:17Free Sector Technology
- 7:17System Bus Access Block
- 8:12GT Performance
- 9:03System View
- 9:40System View Benefits
- 10:06RTT and System View
- 11:02Resources
- 11:52SystemView Host
- 15:40Complete Solution
- 16:00Download Example
- 16:58Summary
- 18:08Questions
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