Chipyard and FireSim End to End Architecture Exploration with RISC V

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" summary

Chipyard assembles Chisel/FIRRTL generators (Rocket Chip, BOOM, accelerators like Hwacha and SHA‑3) plus software images and RTL flows so a single config emits Verilog for RTL sim, FPGA builds or VLSI. FireSim uses a Golden Gate compiler and a manager to produce deterministic, latency‑accurate FPGA‑accelerated simulators on EC2 F1, decoupling host time to run real Linux workloads; teams scale to ~1,024‑node datacenter models and see 6–150 MHz effective target rates depending on IO. Hammer automates PDK/tool scripts for tape‑out; several test chips and industry uses succeed.

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" chapters (33)

1. 0:00Start
2. 1:27The Challenges
3. 4:19Agenda
4. 4:55Shipyard Basics
5. 9:20What Is Chisel
6. 10:44Chisel Is Backwards Compatible
7. 14:46What Is Rocket Ship
8. 16:26The Structure of Soc
9. 17:15Rocket Inorder Core
10. 18:00Rocketship Coprocessor Interface
11. 21:22Rock Accelerator Interface
12. 26:06Challenges Configuring Generators
13. 33:39Repository Structure
14. 35:47Custom Config
15. 45:53They Allows You To Add Your Own Particular Files To Run Software or Build a Simulator and You Can Basically Dump It all in One Place so that When You Create a Design You Have All the Collateral in One Place That You Can See It So To Go a Little Bit into More Depth about the Vera Log Flow so We Created this Configuration That Parameterised Is the Chisel so You Have Your Configuration and all You Different Particular Ip Blocks So in this Case You Have Your Sha-3 Configuration Then You Actually Want To Elaborate into Fertile so You Want To Take that Chisel Representation
16. 51:15And So the Role of Fire Sim in Reducing the Cost of Building a Chip Is by Trying To Make You Know To Try and Build a Better Full System Simulator so Dupree Silicon Validation Verification and Software Development Which Are the Sort of Quintessentially the Largest Costs in Building a Chip So if You Were Going To Build an Ideal Full System Simulator Today Obviously You Know We Wanted To Run As Fast as Silicon It Would Have To Be As Detailed as Silicon so It Was a Useful Debug Target and Then We Could Do Useful Pre Silicon Validation Ideally You Would Have All the Benefits of a Software Simulator Right It Should Be Easy To Debug You Should Get Full Visibility over a Machine Which Should Be Able To Recompile for It Instantly
17. 51:45It Would Have To Be As Detailed as Silicon so It Was a Useful Debug Target and Then We Could Do Useful Pre Silicon Validation Ideally You Would Have All the Benefits of a Software Simulator Right It Should Be Easy To Debug You Should Get Full Visibility over a Machine Which Should Be Able To Recompile for It Instantly and Most Importantly if We'Re Going To Bring Down an Ori It Needs To Be Cheap Right and So the Adage Goes You Can Only Pick Two or Maybe Two and a Half of these
18. 55:21The First of Which Is Fire Sim Builds Something like a Hardware Emulator We'Re Not Building Prototypes Here We'Re Not Going To Just Be Synthesizing a Rocket Ship into What's and I'Ll Explain How that Happens in a Moment We Use Cloud Fpgas That's Not Strictly Speaking Required but It Has Lots of Upside for One It Gives Us as Researchers Access to Very Large Fpga I Would Be Very Hard for Us To Buy Otherwise Right and of Course It's an Elastic Supply So if You Want To Run Spec in Parallel on 48 Different Simulators You Can Do that There's no Way We Could Buy 48 of these Fpgas and another Nice Feature Is It Makes It Really Easy To Collaborate because if I Build a Bit Stream
19. 1:01:46This Is Something That I Think It's Relatively Novel for You Know an Open-Source Academic Offering and of Course once You Have the Means To Stall Simulation Locally on Say at the Fpga Well You Can Tie an Arbitrary Number of Fpgas Together and that Was the Basis for Our Escape a Perimeter Thousand a Thousand no Data Center Right You Use a Lot of Fpga Is You Tie Them All Together in this Latency Insensitive Graph Now You Can Cycle Actually Model Our Data Center and Again We'Re Using this this Decoupling Trick if You Want to Instrument Your Machine without Changing Its Behavior You Can Just Stall the Clock
20. 1:04:54And Then Run Spec on all of those Points in Parallel and because We Have this Ability To Stall a Clock We Have the Privilege To Add a Whole Bunch of Useful Verification and Debugging Tools Right So the First of Which Is Assertion Synthesis and Print Synthesis So in Chisel Much like You Know Very Log There Are Sort of Structures That You Use To Assert Certain Predicates Are True or To Print to a File for Instance We Can Synthesize those and Pull Them off the Fpga We Have the Ability To Automatically Integrate Il a's Which Are Sort Of Silences in Circuit Debuggers
21. 1:06:53So I'M Not Going To Go into Too Much of the Detail Here but Spice To Say Is if You Have a Design in Shipyard You Can Simulate It in Fire Suit so up until this Point I'Ve Sort Of Been Focusing More on the Process through Which We Take a Design and We Map It into this Deterministic Form the Piece That's Responsible for that Is Called Golden Gate Which Is Our Compiler It's a Fertile Compiler It Automatically Converts a Slick Rtl into Sources To Build this Fpga Accelerated Simulator the Second Piece Is What We Call the Manager
22. 1:07:42There Are Sort Of a Few Key Directories You Need To Be Aware of First Which Is Sim this Is Where the Compiler Is this Is Where You Basically Put Together Your Simulator and Do Rtl Simulations of the Simulator Itself before You Decide To Build a Bit Stream There's a Make Based Build System Here and this Is How You Tell Golden Gate What Sort of Design You Want To Build a Simulator for Deploys Where the Manager Lives this Is Where You'Ll Be Running out of if You'Re Running Simulations on Ec2 in Platforms We Have Project Definitions Which Are Going To Sort of Host the Vera Log We Generate
23. 1:20:57State Snapshotting and Replay
24. 1:21:56Energy Modeling
25. 1:25:23Debugging
26. 1:26:36Ila Integrated Logic Analyzer
27. 1:29:51Alternatives Debugging Technique
28. 1:31:24Synthesizable Assertions
29. 1:38:48Cons
30. 1:39:14Auto Counter
31. 1:43:05Recap
32. 1:43:47Multi Fpga Network Simulation
33. 1:46:30Super Node

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