An Open and Coherent Memory Centric Architecture Enabled by RISC V

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" summary

An open coherence protocol (Omni-Ext) implements TileLink 1.0 over standard L2 Ethernet, demonstrated on two Xilinx FPGAs and a Barefoot/Tofino switch as an eight-core two-socket system, running at 50 MHz and showing about 4 microsecond latency through a switch. The repo moves to CHIPS Alliance and publishes a spec plus detailed state transition diagrams (~250 RTL states), an EMU emulator for laptop development, and scripts for VM-based switch simulation; an SoC tapeout is planned.

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" chapters (14)

1. 0:00Introduction
2. 1:17What is IST
3. 4:53Performance Measurements
4. 6:04Houdini
5. 6:49Coherent Protocols
6. 9:58PILink
7. 13:52New Github
8. 14:29Software
9. 15:58L1 specification
10. 16:48State transition diagrams
11. 17:29EMU
12. 18:24How to use EMU
13. 18:54Sim for Simulation
14. 19:24Virtual Switch

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