How to Secure a RISC V System in 90 minutes From Single Core MCU to Mixed

on YouTube ↗01h 37m

" summary

Hands-on pipeline shows an open Rocket-based SoC built from GitHub, an FPGA bitstream flashed to an X300 board with Vivado and OpenOCD, debugged with GDB/Eclipse, and running a multi‑zone nano‑kernel that isolates FreeRTOS, picoTCP and wolfSSL into separate executables. Policy is PMP entries loaded into the core at boot, the trusted base compiles to 1.6 KB trusted core, context switches take ~121 instructions, and a demo moves a robotic arm — the system boots, enforces faults, and works end-to-end.

AI-written summary · about

" chapters (10)

1. 0:00Start
2. 11:33adapt the shell
3. 32:15the lock bit
4. 35:55connect an embedded device to the internet
5. 39:31create separation inside the system
6. 52:10bsp what is a bsp board
7. 54:11map pieces of your hardware to each zone
8. 1:04:28buffer overflows
9. 1:18:20break the system in pieces
10. 1:25:26the size limit for ipc messages

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