Keynote: NVIDIA’s secure RISC-V processor

on YouTube ↗16m

" summary

NVRISCV is a second generation RISC-V core with tightly coupled crypto accelerators (SHA, AES, RSA, ECC), TRNG and secure key storage and it replaces a proprietary Falcon core that shipped billions of units. Hardware enforces partitions via a machine‑mode separation kernel and manifested hardware policy, extends PMP from 16 to 32 PMP entries, adds IOPMP to isolate DMA and engines, implements dual-core lockstep with a shadow core and a hard stop instruction, experiments with top‑bit pointer tagging, and uses Ada/SPARK plus Cadence/Synopsys formal tools for proofs.

AI-written summary · about

" chapters (5)

1. 0:00Introduction
2. 1:41Where does NVIDIA use embedded processors
3. 3:38Challenges
4. 6:46Security
5. 14:38Summary

" related talks

• 16mKeynote: RISC-V Security - Current Initiatives and Future TrendsHelena Handschuh · RISC-V Summit North America 2024
• 19mAn Open Source Approach to System SecurityHelena Handschuh · RISC-V Summit 2019
• 15mKeynote: Securing the Final Frontier: RISC-V® in Space and Critical InfrastructureTed Speers · RISC-V Summit North America 2025
• 21mRISC-V International Security OverviewHelena Handschuh · RISC-V Forum: Security 2021
• 13mRISC-V: Securing the Future of Open Source ComputingAndrew Dellow · Spring 2022 RISC-V Week — RISC-V International Day
• 13mUsing RISC V As a Security Processor For DARPA CHIPS And Commercial IoTMark Beal · 7th RISC-V Workshop 2017
• 09mThe Future of Embedded Security with RISC-VDavid Kerr-Munslow · RISC-V at embedded world 2024
• 16mTrusted RV: Trusted Execution Environment, Secure Coprocessor, and their Program...Kuniyasu Suzaki · RISC-V Forum: Security 2021