Noel-V: A New High-Performance RISC-V Processor Family

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" summary

Noel‑V is a 64‑bit RISC‑V core family delivering a dual‑issue 7‑stage pipeline that boots Linux and measures about 4.69 CoreMark/MHz on initial FPGA hardware. The released HPP64 implements RV64GCBNH, L1 I/D caches up to 16 KB, virtually indexed physically tagged lines, and snooped coherence; L2 cache and fault‑tolerant extras are available under commercial license. The FPU in the GPL release is small and multi‑cycle; a commercial pipelined DRFPU gives one‑per‑cycle throughput with 4‑cycle latency (divide 16, sqrt 24).

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" chapters (8)

1. 0:00Introduction to NOEL-V
2. 1:24Licensing and IP ecosystem
3. 2:28NOEL-V design environment
4. 2:51NOEL-V core features
5. 3:54Floating-point unit details
6. 4:57Pipeline architecture
7. 6:41MMU and cache design
8. 8:28Debug and configuration