Software Development for 64-Bit RISC-V Processor Verification

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" summary

A C++ reference model called Nigama C++ model implements RV64IMAFD (unprivileged and privileged) with MMU, FPU, exceptions and debugger hooks and runs in lock-step with the DUT over Ethernet step-lock comparison. The DUT (FPGA or HDL sim) sends bundled results of >2000-instruction packets, Nigama replies with ACK, and mismatches cause an error log that prints PC plus register/memory/CSR address and value so engineers reproduce bugs on an HDL simulator or via disassembly. Used to verify an out-of-order single-core RV64IMAFD; multicore extension is in progress.

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" chapters (4)

1. 0:00Introduction and CDAC overview
2. 4:01Software verification process
3. 7:09Nicoma reference model
4. 15:30Verification speed and benefits

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