The RISC-V Verification Ecosystem with Open Standards and Commercial Tools
summary
RISC-V verification requires scaling beyond ad hoc tests to meet one quadrillion cycles of coverage estimated for modern CPUs, a number that RTL simulation at kilohertz or single emulators at megahertz cannot reach in realistic time. The ecosystem pushes reusable verification IP, functional coverage and golden reference models (Imperas models used as oracles), instruction-retire lockstep and RVVI interface (Apache‑licensed) for plug‑in testbenches, plus formal and asynchronous lockstep to find hard corner bugs.
AI-written summary · about
chapters (9)
- 0:00Introduction and speaker welcome
- 1:02Verification ecosystem importance
- 3:52Verification challenges in modern systems
- 7:47Silicon success risks and costs
- 8:49Collaboration in verification
- 10:12Empiris role in RISC-V verification
- 11:58Verification techniques progression
- 13:23RISC-V verification interface RVVI
- 14:27Summary and call to action
related talks
23mThe Continuum of RISC-V Compliance and Verification Testing
24mRISC V Processor Verification based on Open source Framework
10mDemo: Introduction to RISC-V Verification with the Open Standard RVVI (RISC-V Verifi...
46mRISC-V Open ISA’s Shock Wave of Processor Innovation Causing Seismic Shift
13mIntroduction to RISC-V Processor Verification
47mTutorial: Choosing Appropriate Verification Techniques for Desired RISC...
23mOpen Source Verification Platform for RISC V Processors
25mRISC-V System-level Certification from Verification Foundations
