~/talk

Commercial Adoption of CORE-V Open-Source RISC-V Cores - Lessons Learned

Talkat RISC-V Summit Europe 2023 · 2023-06-05..06-09· [testing]
slides:none on file

OpenHW’s CORE‑V family provides SystemVerilog RISC‑V cores with a UVM verification bench that runs on commercial EDA simulators and has 54 GitHub project repos, ~1,627 forks and >4,000 stars. The CV32 and CVA6 variants hit silicon >40 times and the 32‑bit lineage counts hundreds of millions of cores in production. Toolchain enablement includes an Eclipse IDE, Embecosm compilers and Digilent Nexus/Genesis FPGA demos; a GF 22FDX Core5 MCU with embedded FPGA is in fab and a group‑buy is open. Key lessons: SystemVerilog and UVM, Apache + Solderpad licensing, focus on IP quality and ecosystem.

AI-written summary · about

  1. 0:00Introduction
  2. 1:24Ecosystem formation
  3. 4:02Growth and projects
  4. 6:19Development and statistics
  5. 8:41Adoption and real-world use
  6. 10:04Lessons: Permissive licensing
  7. 11:54Lessons: IP quality and trust
  8. 13:17Enablement and conclusion
~/search
type to search 6,249 conferences, 138,987 speakers and 185,172 talks
~/help
cmdctrl k
search every conference, speaker and series
/
focus the filter search
h
home
c
conferences
s
speakers
e
series
t
light / dark — the status bar button does the same
?
this help
esc
close this, then clear every filter — or just the search, while you are typing in it

Ignored while you are typing. Pages without a filter rail have no search to focus.