Commercial Adoption of CORE-V Open-Source RISC-V Cores - Lessons Learned
summary
OpenHW’s CORE‑V family provides SystemVerilog RISC‑V cores with a UVM verification bench that runs on commercial EDA simulators and has 54 GitHub project repos, ~1,627 forks and >4,000 stars. The CV32 and CVA6 variants hit silicon >40 times and the 32‑bit lineage counts hundreds of millions of cores in production. Toolchain enablement includes an Eclipse IDE, Embecosm compilers and Digilent Nexus/Genesis FPGA demos; a GF 22FDX Core5 MCU with embedded FPGA is in fab and a group‑buy is open. Key lessons: SystemVerilog and UVM, Apache + Solderpad licensing, focus on IP quality and ecosystem.
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chapters (8)
- 0:00Introduction
- 1:24Ecosystem formation
- 4:02Growth and projects
- 6:19Development and statistics
- 8:41Adoption and real-world use
- 10:04Lessons: Permissive licensing
- 11:54Lessons: IP quality and trust
- 13:17Enablement and conclusion
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