Unlocking Open Source RISC-V SoC Verification
summary
CHIPS Alliance integrates Verilator changes so Verilator 5.x can run event‑driven SystemVerilog testbenches by adding dynamic scheduling (first done as a threads prototype then reimplemented with C++20 coroutines to reduce the slowdown from hundreds× to a negligible overhead). A UHDM SystemVerilog frontend is in use to parse/synthesize designs (Ibex simulated in late 2020). Work on UVM features (constraint randomization, fork/join, event vars) is underway; mixed VHDL and SystemC->UHDM paths are planned.
AI-written summary · about
chapters (8)
- 0:00Introduction to open source RISC-V
- 3:16Chips Alliance and open source flows
- 8:50Open source verification challenges
- 10:14Verilator dynamic scheduling for UVM
- 15:10UHDM and system verilog support
- 17:57Next steps for UVM in Verilator
- 20:25VHDL and SystemC support plans
- 22:32Q&A and closing remarks
related talks
21mOpen Source Digital Design Tooling Updates
24mOpen source RTL verification with Verilator
20mCHIPS Alliance: towards a unified open source ASIC design & DV workflow
22mOpen source design testing and verification with UVM and Verilator
12mUnityChip Verification: Open-Source RISC-V Verification at BOSC
23mOpen Source Verification Platform for RISC V Processors
13mIntroduction to RISC-V Processor Verification
24mRISC V Processor Verification based on Open source Framework