Open source RTL verification with Verilator

on YouTube ↗24m

" summary

Verilator now supports timing-aware simulation via a new coroutine scheduler and compiled UVM SystemVerilog constructs so UVM code transpiles to C++ and runs in public CI; parameterized classes, process control and most SystemVerilog features are implemented, though earlier runs produced incorrect results until fixes. Constraint randomization is handled by SMT-LIB2 constraint export sent to external solvers, and timing work ships as Verilator 5 timing-aware scheduler. A Calyptra UVM testbench runs bit-for-bit identical to a proprietary simulator.

AI-written summary · about

" chapters (9)

1. 0:00Introduction and motivation
2. 1:41Verilator and UVM goals
3. 4:21Implementing timing support
4. 7:36Key feature contributions
5. 11:05Constraint-based testing
6. 13:50Debugging tools
7. 15:36Calyptra UVM demonstration
8. 17:00Future work and roadmap
9. 21:18Q&A session

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