Transparent Checkpointing for Fault Tolerance in RISC-V
summary
DMTCP is ported to RISC‑V Linux on a BeagleV PolarFire SoC and resumes simple and TCP‑socket C++ programs from checkpoints (a counter restarts at the saved value after a 5s checkpoint). Porting changes are ~20 lines of inline assembly plus adjusting TLS logic because RISC‑V points the thread pointer to the end of the TCB; work takes about two weeks. Major blockers: DWC missing on RV32 forces slower malloc+mutex fallbacks, pthread join currently triggers a segfault, and the 2GB board memory makes debug/run slow.
AI-written summary · about
chapters (13)
- 0:00Transparent checkpointing intro
- 1:49Middleware need in RISC-V
- 3:13Checkpointing use cases
- 4:21DMTCP for transparent checkpointing
- 6:11DMTCP fault tolerance architecture
- 7:14Porting DMTCP to RISC-V
- 8:19Basic checkpointing demo
- 9:33Multi-process checkpointing demo
- 10:18RISC-V support changes in DMTCP
- 12:07Lack of double-word CAS
- 13:54Hardware limits and debugging delays
- 14:14Pthread and multi-threading issues
- 16:55DMTCP and RISC-V future
related talks
21mScaling Data Analytics Via Confidential Computing on RISC-V
24mSystem Level Security Verification of RISC V Based SoCs
09mDemo: Facilitating Trusted Application Migration to RISC-V
47mA Security RISC? The State of Microarchitectural Attacks on RISC-V
01h 05mConfidential Computing for RISC-V-based Platforms
01h 37mHow to Secure a RISC V System in 90 minutes From Single Core MCU to Mixed
21mUtilizing RISC-V Trace Standards for Efficient Bugfixing and Profiling
52mEnabling New Security Frontiers: Deep-Dive Into Implementing Confidential Computing on RISC-V