Riding The Wave: Building Wave Pipelines in FPGAs
summary
Builds a two‑stage wave‑pipelined cellular‑array multiplier on Xilinx 7‑series FPGAs using SpinalHDL and manual placement with RLOC origin / RPM constraints, packing one multiplier cell per slice and coaxing Vivado to route. Measured combinational delays are 15.5 ns max and 12.7 ns min (about 2.7 ns skew) and a stable operating point near ~130 MHz, with future optimisations planned using carry‑chain routing to cut interconnect skew.
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chapters (10)
- 0:00Introduction
- 0:27Defining wave pipelines
- 2:41Motivation and methodology
- 3:29Classical vs wave pipelines
- 5:55Research and implementation
- 7:52FPGA mapping and routing
- 10:49Results and analysis
- 12:45Future improvements
- 14:13Pros and cons
- 15:50Q&A and discussion
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