Teaching Modern EDA using a Tapeout-Centric University Course
summary
Course runs four semesters with ~60 students and gets every student to tape out a design using tiny tapeout (≈$150 MPW slots) or a shared MPC chip built on the SkyWater 130 PDK and Caravel padframe. Curriculum uses OpenLane, Yosys, nextPNR, cocotb and ULX3S FPGAs, weekly labs, and mandatory design and verification milestones. Students implement tiny STA and DFT tools (hundreds of Python lines), discover how Verilog style shifts critical paths, exercise metastability demos, and receive a bring‑up PCB to validate several post‑silicon projects that do work.
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chapters (11)
- 0:00Introduction
- 0:53Motivation
- 14:23Tapeouts
- 14:35Projects
- 15:00PostSilicon
- 15:13Student Projects
- 15:34Lessons Learned
- 16:28Start Early
- 16:56Contact
- 17:24QA
- 20:27Outro
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