Teaching Open Silicon Design in a Quarter: Using Cloud-based Open Agile EDA Platform
summary
A quarter-long course builds a full open-source RTL-to-GDS pipeline using Yosys, SV2V, iEDA/IDA (11 components, ~300k LOC) and IHP130/SkyWater nodes, delivered on a scalable cloud platform that aims to support ~500 students with 5–10 TAs. The team implements an RTL2GDS flow and demonstrates it on a retroSoC 32-core testchip with backend, timing and layout completed and a 110 nm tapeout submitted; the cloud runs a full build in ~25 minutes.
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chapters (14)
- 0:00Introduction
- 0:52Project Overview
- 2:20Why we want to teach Open Silicon Design
- 4:06Key Design Considerations
- 5:09Infrastructure
- 6:19Community
- 7:44AI Agent
- 8:14Retro SOC Design
- 9:15Retro SOC Evaluation
- 9:47IDA
- 16:20AIDA
- 17:12AIDA in 2020
- 18:45Contact Information
- 18:59Questions
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