bsg_pearls: Effortlessly Synthesizable Building Blocks That Work Right Out of the Shell
summary
A library of mid-level, silicon‑proven modules (clock generator, delay line, SDR/DDR/LPDDR links, LPDDR controller) ships with SystemVerilog, synthesizable testbenches, vendor‑agnostic TCL constraints and placement guidance; each pearl is runtime‑configurable and isolation‑constrained so interfaces harden early. The clamshell flow uses local clock gens and source‑synchronous links to avoid a global clock tree, cutting top‑level APR turnaround from about two days to ~30 minutes in one example. Tool collateral is Python + Sherlock‑derived Tcl dictionaries and is on GitHub. clock generator SDR links source‑synchronous
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chapters (9)
- 0:00BSG Pearls intro
- 1:03What BSG Pearls solves
- 3:55Glue code challenges
- 5:38BSG Pearls IP blocks
- 7:25Traditional ASIC limits
- 9:10Clamshell methodology
- 11:18Tool-agnostic flow
- 13:28BSG Pearls status
- 14:32Q&A
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