On a Quest for the Ideal HDL(s) for Makers and Hobbyists
summary
Discusses how common RTL HDLs (Verilog/VHDL-style) force implicit clock/reset models and confusing blocking vs non‑blocking semantics, which break small maker projects, create timing spaghetti, and hinder reuse. Reviews how simulation‑only constructs often won’t synthesize, verification tools are fragmented, and toolchain hassles dominate; highlights newer high‑level hardware languages and toolchains that maintain silicon‑close abstractions and can generate working, testable FPGA designs.
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chapters (6)
- 0:00HDL frustrations
- 3:10Ideal HDL traits
- 8:15High-level synthesis
- 12:54Pipelining trade-offs
- 16:54Simulation & verification
- 19:20Conclusion
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