Visions of the future (Clash 1.0)
summary
Clash 1.0 compiles high-level Haskell into VHDL and SystemVerilog and now implements configurable clock domains with selectable rising or falling edges, turning functional descriptions into real hardware outputs. The project treats functions as the native circuit primitive and aims to build a minimal functional core then add targeted extensions so the same compiler can map to different backends — classic FPGA flow today and future backends like GPUs or graph/accelerator architectures.
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