Raising the level of abstraction in digital design with Chisel3 and FIRRTL
summary
A concrete workflow is described: Chisel3 programs generate FIRRTL which lowers to low FIRRTL for reusable compiler transforms, emitting Verilog for simulators and tools; Diplomacy negotiates parameters bidirectionally (cardinality, address maps, PMP) so generators auto-adjust topology and address widths; FPGA shells produce wrappers and constraint files so designs map to multiple boards. This stack is used in Rocket Chip and at SiFive, supports clock crossings and Verilog black boxes, and is already deployed in production flows.
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chapters (12)
- 0:00Start
- 1:51Agile Hardware Design
- 5:20Chisel
- 9:24Borrow good ideas from software, build a compiler!
- 10:13FIRRTL: Flexible Intermediate Representation for RTL
- 11:04Building an Ecosystem
- 15:06Negotiation
- 15:56What kinds of Parameters Can Be Diplomatic?
- 16:34Real Rocket-Chip Diplomacy Graph
- 17:04Parameterization + Decoupling Design from Implementation
- 18:47FPGA Shells
- 19:57Get Involved!
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