Jack Koenig
where else to find them
what they talk about
where they keep going back
- ORConf3 editions2018–2025
on a stage with
never shared a talk
who talks about the same things
- Staf Verhaegen9 talks
- Karol Gugala12 talks
- Olof Kindgren14 talks
- Rob Taylor4 talks
- Todd Strader3 talks
- Frans Skarman7 talks
| title | conference | date |
|---|---|---|
| 10 Years of Chisel | ORConf 2025 | 2025-09-12 |
Fifteen‑year project with ten years of direct involvement; Chisel 7.0 ships new features: probes (XMRs), properties (metadata), layers that can lower to… | ||
| Chisel 6 and beyond | Latch-Up 2024 | 2024-04-19 |
Chisel 6 moves the FIRRTL implementation to an MLIR-backed Circuit/ferTool pipeline for much faster, lower-memory compilation and faster feature work. New… | ||
| Designing and Building Modern Modular SoCs w/ Open Source Federation Tools | RISC-V Summit 2019 | 2019-12-09 |
Federation tools bundle three open-source utilities for modular SoC construction and reproducible onboarding: wit, do, wake. The flow uses Docker, wit to… | ||
| What's new in Chisel | ORConf 2019 | 2019-09-27 |
Chisel 3.2 reaches second release candidate with a breaking upgrade from 3.1 and a bumped Rocket Chip branch available for testing. Key additions include… | ||
| Onboarding Verilog Peripherals to Rocket Chip | ORConf 2019 | 2019-09-27 |
Rocket Chip integration workflow that automates Verilog IP onboarding using a machine-readable DO manifest plus repo orchestration with wit repo manager and… | ||
| Raising the level of abstraction in digital design with Chisel3 and FIRRTL | ORConf 2018 | 2018-09-21 |
A concrete workflow is described: Chisel3 programs generate FIRRTL which lowers to low FIRRTL for reusable compiler transforms, emitting Verilog for simulators… | ||
| nothing matches | ||