10 Years of Chisel
summary
Fifteen‑year project with ten years of direct involvement; Chisel 7.0 ships new features: probes (XMRs), properties (metadata), layers that can lower to SystemVerilog bind, format strings, module prefixing, reduced memory use, and improved stack traces plus a statically linked Fur tool and experimental inline unit tests. Emphasis is on practical usability: one‑download Scola/CLI examples, browser demos (Surfer, Spade), source locators for mapping back to Scala, and careful Verilog naming to make debugging and verification actually work.
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chapters (9)
- 0:00Introduction
- 1:05Chisel 7.0 highlights
- 2:08HDL design principles
- 3:54Ease of use in HDLs
- 6:00Syntax and info density
- 7:24Debugability and Source-Level Debugging
- 8:27Good error messages
- 10:13Clean Verilog names
- 12:00Q&A
