Advancing design verification with Verilator
summary
Project progress shows 21 of 33 UVM cookbook examples passing and the tool can now elaborate all of UVM 2017 without workarounds. Recent additions include nested classes, selective fork disabling by label, generic interfaces, and extensive constraint randomization implemented by translating constraints to SMT with Z3-based randomized solving, plus pre/post-randomize hooks and run/constraint modes. Coverage gains add generate/gen block and ternary coverage and separate pos/neg change counters. Post‑synthesis flows gain user‑defined primitive support and compact SAF activity dumps for faster STA.
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chapters (5)
- 0:00Verilator UVM support
- 2:24New verification features
- 3:56Constraint randomization
- 7:23Coverage and simulation
- 9:18Future goals and Q&A
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