Verifying Out-Of-Order RISC-V Vector Extension With Open Source Tools
summary
An open-source verification stack verifies an out-of-order RVV 1.0 implementation (plus BF16, bitmanip, crypto and dot product extensions) by combining Riescue C/D generated stimuli, a forked riscv_dv for updated RVV 1.0 opcodes, and rv_tester cosimulation that compares RTL to Whisper ISS at every instruction boundary. The flow finds bugs in complex micro‑sequences (crossing ROB boundaries, vlen=0 with nonzero vstart, element faults), exercises RCC-style memory consistency for multi-core (2–8 cores per cluster) designs, produces functional coverage, and successfully verifies a high‑performance OOO core.
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chapters (8)
- 0:00Introduction and methodology
- 1:00Verification phases
- 2:39Design architecture overview
- 4:39Directed test framework
- 7:14Compliance testing
- 9:24Randomized testing
- 10:36Simulation and testbench
- 12:40Coverage and conclusions
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