Making CHERI Accessible
summary
LowRISC builds a CHERI-capable Sonata SoC plus an open FPGA evaluation board sold on Mouser and distributed as 100+ boards for experiments, using open PDK45 and OpenRAM. Key results: 70% of Microsoft-era CVEs would be mitigistically prevented, CHERI adds ~57% area to a tiny Ibex core (about 1% of an OpenTitan SOC) versus 42% for PMP, and software porting is small (FreeRTOS networking 147k LOC needs ~6k changes ≈4%; a 6M LOC desktop port changed 0.026%). Performance work yields 2x GPIO latency reduction and 3x HyperRAM throughput with CHERI tag handling. The CHERI Alliance coordinates standardization and tooling.
AI-written summary · about
chapters (10)
- 0:00Introduction to CHERI
- 1:03About LowRISC and open silicon
- 3:34Why memory safety matters
- 6:44CHERI basics and Chariot
- 8:32Sonata development platform
- 10:16Sonata performance improvements
- 11:40CHERI area and code impact
- 14:47Memory bandwidth considerations
- 15:07Call to action and CHERI Alliance
- 16:15Q&A session
related talks
15mSonata: A development platform to enable exploring the use of CHERI for embedded applications
01h 33mHands-on Introduction to CHERI
53mLinux and CHERI: Back to the Future
31mMemory Safety: The Pernicious Challenge
22mIntroduction to Project CHERIoT
17mHardening Linux and FreeBSD on RISC-V with CHERI
10mCHERI in out-of-order microarchitectures
18mWhat’s next for memory safety?