Enabling RISC-V Success: From Design to Deployment
summary
Siemens EDA shows a concrete end-to-end RISC‑V flow: C++ to synthesizable RTL via high‑level synthesis for accelerators, exhaustive formal verification of cores using Questa processor (published bug‑finding case studies), system validation on Veloce platforms scaling to 40 billion gates, and post‑silicon observability with Tessent Ultraite’s embedded functional monitors that cross‑trigger, export data via SDK/APIs, and integrate with existing debuggers and prototyping (workshop demos and in‑field monitoring examples).
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chapters (7)
- 0:00Introduction and overview
- 1:05RISC-V design challenges
- 3:13High-level synthesis for accelerators
- 7:14Processor verification with Questa
- 8:58Veloce platform for prototyping
- 12:12Post-silicon debug with UltraSoc
- 16:32Summary and resources
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