Building Tool Chains for RISC-V AI Accelerators
Talkat RISC-V Summit North America 2024 · on Tuesday, 2024-10-22· at 14:15· Grand Ballroom G (Level 1)·
summary
A working open-source flow that runs PyTorch, TensorFlow and OpenXLA on an emulated RV64 accelerator using QEMU RISC‑V model of a few cores and a memory‑mapped tensor/command register interface, proving early software bring‑up before silicon. Key tools are private use one and execuTorch hooks to intercept ops, and the OneAPI/OpenCL/SYCL route (OneAPI Construction Kit + HAL) to generate host plus accelerator ELF code. Performance tuning around RVV remains hard but the prototype successfully executes and parallelizes large kernels across cores.
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chapters (6)
- 0:00AI system tooling overview
- 3:12Prototyping RISC-V co-processors
- 5:46Implementing the oneAPI framework
- 11:38Construction kit resources
- 12:27Developer community and support
- 15:16Q&A and closing remarks
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