An Adaptive Interrupt Architecture for Extremely Timing-Critical Applications

on YouTube ↗19m

" summary

A scalable interrupt microarchitecture duplicates most general-purpose registers and CSRs and adds a hardware preemption controller plus a per-interrupt lookup table to pick between conventional handling and an immediate ISR path, implemented in silicon and measured to produce about a 30% reduction in total control time. Device drivers expose modified IRQ APIs while keeping applications unchanged, and debug access uses privileged instructions or memory mappings to inspect the duplicated contexts, proving the approach works and remains orthogonal to existing optimizations.

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" chapters (7)

1. 0:00RISC-V at Samsung LSI
2. 4:25Timing-critical challenges
3. 7:10Immediate interrupt handling
4. 9:37Avoiding fragmentation
5. 10:59Adaptive architecture design
6. 13:57Conclusion and summary
7. 15:34Q&A session

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