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Debug Signal Trace: HW Signal Capture in Post Silicon for Debug, Coverage and...

Talkat RISC-V Summit North America 2024 · on Tuesday, 2024-10-22
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slides:none on file

Tenstorrent describes a hardware Debug Signal Trace (DST) that captures selected microarchitecture signals over many cycles and writes compressed packets to on‑chip SRAM or off‑chip system memory, reusing trace funnel/trace sync and parts of the instruction trace encoder. DST timestamps packets to correlate with instruction trace, adds a packet loss bit for integrity, mirrors the RISC-V Trace Control Interface registers for easier adoption, and reports about 30% memory reduction from compression while enabling coverage and performance analysis beyond failure snapshots.

AI-written summary · about

  1. 0:00Introduction to DST
  2. 1:42Motivation and problem
  3. 3:35Hardware architecture
  4. 6:14Trace packet structure
  5. 7:56Programming and decoding
  6. 10:05Use cases beyond debug
  7. 11:51Selecting debug signals
  8. 13:18Standardization and future
  9. 14:22Q&A session
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