Aggregation Optimization for SIMD Everywhere from ARM Neon to RISC-V Vector and Crypto Extensions

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" summary

Enhanced SIMDe headers provide direct ARM NEON→RVV and RISC‑V crypto mappings and land upstream, implemented as RVV intrinsics in LLVM IR. An LLVM pass called DLSP LLVM pass aggregates many 128‑bit NEON-style ops into wider RVV vectors by loop unrolling, SLP-style isomorph detection, data‑access functions, shuffle insertion and dead‑element elimination. Evaluation on Spike (RVV vlen 256, LLVM 17) with XNNPACK-ish kernels shows dynamic‑instruction reductions in the range 4.35×–11.02× speedup versus naive translation.

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" chapters (5)

1. 0:00Introduction to SIMDe
2. 2:04SIMDe implementation
3. 3:07Crypto extension support
4. 7:00Vector aggregation logic
5. 7:48Experimental results

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