Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC...
summary
Packed-SIMD P extension work targets scalar DSP patterns and ships preliminary mnemonics, opcodes, SAIL models, draft docs and POC LLVM/binutils and upstream GCC/LLVM/binutils/GDB support; microbenchmarks use cycle counts and show 86k gates vs 800k gates for packed SIMD versus a VPU and deliver library speedups of 9–16x (general NN ops), ~10x PNET face detection and ~14x CIFAR10 image classification. Design is integer-only with RV64: eight 8-bit lanes / four 16-bit lanes (RV32 halves); Spike/QEMU testing and C/C++ intrinsics are in progress.
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chapters (7)
- 0:00Introduction to scalar SIMD
- 2:09Benefits for embedded systems
- 3:36Target markets and use cases
- 5:34Specification development
- 7:24Tooling and ecosystem status
- 8:08Performance benchmarks
- 11:04Questions and answers
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