Networking-Native RISC-V Processor for Datacenter

on YouTube ↗18m

" summary

A RISC‑V I8500 core is built for line‑rate packet work: RVB23 with SV39/SV48, big‑endian execution, an in‑order three‑issue pipeline and 4‑way SMT that lets one core plus threading double packet throughput versus a Cortex‑A53 in the authors’ Ethernet routing benchmark. DMA delivers headers into local scratchpad with a 3‑cycle header load, an IOCU provides coherent accelerator attachment, and cluster configurations show over 5x scaling moving to six cores with four threads each. Atlas Explorer virtual platform supports the performance modeling.

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" chapters (7)

1. 0:00Introduction to data centers
2. 1:57Data processing units
3. 2:58MIPS i8500 architecture
4. 5:35Hardware multi-threading
5. 7:57Performance benchmarks
6. 11:09Use cases and data flow
7. 16:01Simulation and conclusion

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