Boosting Video Codec With RISC-V Vector Extension

on YouTube ↗20m

" summary

Hardware and software co-design uses ZvZip for in-register reordering (reducing instruction count by about one third), Zvabd for SAD/SATD (about 20% per-op win), and heavy RVV permutes plus lmul-aware scheduling, ping-pong buffering and a hybrid-wide execution pipeline to avoid idle lanes. More than 70% of the top operators gain speed, many show 40–80% cycle reductions, and integrated system optimizations yield 408% speedup for x264 and 430% for x265 versus the unoptimized baseline.

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" chapters (6)

1. 0:00Introduction
2. 2:07Video codec workloads
3. 7:13RISC-V vector gaps
4. 11:09FastTrack extensions
5. 15:28Hardware and software co-optimization
6. 19:30Performance results

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