CVA6-CHERI - An Open-source RV64Y Implementation for Commercialization
summary
Implements CHERI on CVA6 as an RV64Y-compatible core, moving from an initial 58% logic overhead and 23% cycle-time penalty in the research prototype to refinement targeting 35% logic overhead at original frequency; adds a capability logic unit, widened 129-bit registers and memory paths, a midstream capability-mode switch, and a single-owner PCC-bounds scheme that cuts execute-area by ~17%. Verification uses Symbiosis equivalence checks (5 bugs found) and a fully pipelined test rig; prototype meets 50 MHz on a Genesis2 FPGA and runs CheriBSD and CHERI toolchain workloads.
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chapters (11)
- 0:00Introduction to CVA6-CHERI
- 1:04CHERI and CVA6 overview
- 2:29Implementation details
- 5:42Mode switch instruction
- 8:54Verification efforts
- 11:00Test rig improvements
- 11:22Area optimization
- 13:31Execute logic consolidation
- 14:54Timing optimization
- 15:16Software support
- 16:18Q&A
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11mDemo: Securely Booting CHERI on a Full OS to Prevent Buffer Overflow Attacks
01h 33mHands-on Introduction to CHERI
11mFast and fine-grained compartmentalisation in CHERI
17mHardening Linux and FreeBSD on RISC-V with CHERI
25mLightning Talk: Protecting Zephyr Against Memory Safety Vulnerabilities With the New CHERI Hardware Architecture