Enhancing OP-TEE for RISC-V: Leveraging IOPMP and Enabling RTOS Integration
summary
Andes extends OP-TEE on RISC‑V by wiring OP‑TEE to PMP/ePMP, MMU page isolation and a new IOPMP protects DMA to block bus-initiator transactions; upstream Linux and a Zephyr RTOS port are demonstrated as working integrations. A separate MCUT secure monitor targets RV32 no‑MMU systems, MCUT requires 16+ PMP entries and adds per‑zone debugging for predictable ECU latency. Secure boot with signed stages and optional SM reconfiguration of PMP entries enforces chain‑of‑trust. OP‑TEE + hardware PMP/ePMP/IOPMP shown integrated
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chapters (7)
- 0:00Introduction and Andis overview
- 4:22OP-TEE framework and security
- 7:14SOC architecture and memory protection
- 10:10OP-TEE Linux solution details
- 11:35OP-TEE secure monitor project
- 12:17MCUT secure monitor for MCU
- 13:45Q&A session
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