Unlocking 15% More Performance: A Case Study in LLVM Optimization for RISC-V

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" summary

Upstream LLVM gains measurable real‑world wins: a new scheduling model for the space mak 60 plus a microbenchmark latency tool corrects instruction latencies and hides loads, yielding up to 16% SPEC2017 speedup on a Banana Pi BPI F3 board; an SLP/vectorization fix across function calls removes spill-induced slowdowns and reaches ~12% win on affected benchmarks; enabling IPRA to avoid prologue/epilogue spills trims register pressure and gives smaller consistent wins (around 0.5–3%).

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" chapters (6)

1. 0:00Introduction and project overview
2. 1:27Scheduling model for X60
3. 5:02Vectorization across function calls
4. 7:52IPA support for RISC-V
5. 9:20Key takeaways and conclusions
6. 12:54Q&A session

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