Making LLVM RISC-V Compiler More Performant for Everyone

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" summary

LLVM RISC-V work targets concrete wins: add an out-of-order scheduling model (upstream has only Rocket, SiFive S7 and a 32-bit MCU model; ARM has 20+), implement GlobalISel beyond integers, and build multiple RVV auto-vectorizers plus tuned cost models (iterate kernels, compare estimated vs measured speedups, improve Pearson correlation and reduce false positives/negatives). Uncounted loops already vectorize on hardware using RVV fault-only-first loads (string-compare example works), and combine static MCA + dynamic tracing to predict real performance.

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" chapters (13)

1. 0:00Introduction
2. 0:11Overview
3. 2:00Community Contributions
4. 2:58Scheduling Models
5. 4:16Why more scheduling models
6. 5:21Global instruction selection
7. 7:05Autovectorization
8. 8:57Cost Model
9. 11:09Vectorization
10. 12:26String Compare
11. 14:30Polyal
12. 15:35CompPower
13. 16:35Summary

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