The RISC-V Vector Cryptographic Extensions in the Real World
summary
RISC‑V Vector Crypto Extensions add concrete primitives for AES, GHASH, SHA‑256/512, SM3/SM4 and associated bit ops; designs target single instruction per AES round and a dedicated GHASH opcode that saves about 10–15 instructions versus carry‑less sequences. SHA‑512 and SM3 update 256 bits of state per instruction while competitive ISAs do ~28 bits. Implementations hit practical latencies of three–four cycles, and optimal code uses full vlen width, multiple vector pipes, interleaving and multi‑buffering; carry‑less multiply and zvb/zvk are optional in RVA‑23.
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chapters (7)
- 0:00Introduction to RISC-V Vector Crypto
- 1:50Confidentiality and Integrity Algorithms
- 3:40Data Independent Execution Latency
- 5:31Optional Vector Crypto Extensions
- 9:26Performance Advantages of Instructions
- 12:17Writing High-Performance Crypto Code
- 16:58Q&A Session
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