Why RISC-V Through ISA Customization Demonstration
Talkat RISC-V Summit North America 2023 · on Tuesday, 2023-11-07· at 14:30· Expo Hall - Exhibit Hall A - Demo Theater·
summary
Demonstrates RISC‑V ISA customization using Codasip Studio to add new instructions, rebuild the SDK and generate IA/CA models and RTL; a two‑instruction pattern is collapsed into a single mask instruction that appears in the disassembly and cuts that pattern’s dynamic count by about 5.1%, CPI drops from roughly 1.25 to 1.14 after adding simple branch prediction, and adding a parallel multiplier cuts CoreMark instruction stream from ~73M to ~30M; the toolchain successfully compiles, profiles and emits Verilog.
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chapters (8)
- 0:00Introduction to RISC-V customization
- 1:04Performance equation and core modification
- 3:09Setting up the demo environment
- 17:09Collapsing instructions for performance
- 21:48Reducing CPI with branch prediction
- 31:54Adding a multiply compute element
- 53:34Creating a MAC instruction
- 1:05:31Q&A and summary
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