Design for Differentiation: Architecture Licenses in RISC-V
summary
Codasip presents an end-to-end way to change RISC-V ISAs: a high-level processor description language Codal and generator Codasip Studio that produce SystemVerilog, compilers, simulators, debuggers and verification environments from one source. Company claims first commercial RISC-V core in 2015 and over two billion shipped devices. Workflow supports RTL tweaks and ISA extensions, reuses baseline cores, speeds prototyping, and the vendor says it grants architectural-licensing freedom without extra architecture fees.
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chapters (13)
- 0:00Introduction and company overview
- 1:24Standard IP licensing model
- 2:26Differentiated designs with Studio
- 3:51Can vs may modify processor architecture
- 4:53RISC-V open standard benefits
- 6:37Challenges of modifying RTL
- 7:41Codal and Studio tool capabilities
- 8:23Codal language simplicity
- 9:05High-level processor design in Codal
- 10:52Human-readable generated RTL
- 11:12Starting from baseline RISC-V cores
- 11:52RISC-V promise and Kodasip solution
- 12:34Call to action and booth visits
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