NOEL-V, a Configurable 32-Bit and 64-bit RISC-V IP
summary
Configurable RISC‑V IP that implements RV32I–RV64GC profiles, available under GPL or commercial license, and shipping with GCC/LLVM toolchains, a low‑level German debugger and Ashling IDE support. IP includes fault tolerant FT options (EDAC, scrubbers, system reaction), AHB/AXI interfaces, L2 and optional L3 caches, and a hypervisor extension demonstrated with Fentis. Deliverables range from FPGA bitstreams to a single‑core testchip and a 16‑core GR7xV silicon design, with the core silicon proven on 28 nm and radiation tested for space use.
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chapters (7)
- 0:00Introduction to NOEL-V
- 1:06Ecosystem and licensing model
- 5:05NOEL-V processor core overview
- 8:43Fault tolerance in NOEL-V
- 10:07Future developments
- 11:11Multi-core NOEL-V advancements
- 12:15Summary and availability
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