Lightning Talks: Developing RV32G Processor model

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" summary

GSoC'16 project adds a RISC‑V core to the open Arty MPSoC bench so the platform can simulate and verify RISC‑V designs end to end The implementation covers RV32I base (~40 integer instructions) and then added RV32F and RV32D floating‑point extensions, integrates with the MPSoC testbench and improves performance analysis and verification A major engineering hurdle is that upstream toolchains target 64‑bit so a 32‑bit GCC toolchain is built to enable RV32 testing and complete the project

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" chapters (4)

1. 0:00Introduction
2. 0:55Risk 5 Architecture
3. 1:24Why Risk 5
4. 2:35What I contributed

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